october 2009 fdp8n50nz / fdpf8n50n zt n-channel mosfet ?2009 fairchild semiconductor corporation fdp8n50nz / FDPF8N50NZT rev. a www.fairchildsemi.com 1 unifet tm fdp8n50nz / FDPF8N50NZT n-channel mosfet 500v, 8a, 0.85 ? features ?r ds(on) = 0.77 ? ( typ.) @ v gs = 10v, i d = 4a ? low gate charge ( typ. 14nc) ? low c rss ( typ. 5pf) ? fast switching ? 100% avalanche tested ? improve dv/dt capability ? esd improved capability ? rohs compliant description this n-channel enhancement mode power field effect transistors are produced using fairchild's proprietary, planar stripe, dmos technology. this advance technology ha s been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. these devices are well suited for high efficient switching mode power s upplies and active power factor correction. to-220 fdp series g d s to-220f fdpf series g s d g s d g s d mosfet maximum ratings t c = 25 o c unless otherwise noted thermal characteristics symbol parameter fdp8n50nz FDPF8N50NZT units v dss drain to source voltage 500 v v gss gate to source voltage 25 v i d drain current -continuous (t c = 25 o c) 8 8* a -continuous (t c = 100 o c) 4.8 4.8* i dm drain current - pulsed (note 1) 30 30* a e as single pulsed avalanche energy (note 2) 122 mj i ar avalanche current (note 1) 8 a e ar repetitive avalanche energy (note 1) 13.9 mj dv/dt peak diode recovery dv/dt (note 3) 10 v/ns p d power dissipation (t c = 25 o c) 139 50 w - derate above 25 o c1.10.4w/ o c t j , t stg operating and storage temperature range -55 to +150 o c t l maximum lead temperature for soldering purpose, 1/8? from case for 5 seconds 300 o c symbol parameter fdp8n50nz FDPF8N50NZT units r jc thermal resistance, junction to case 0.96 3.1 o c/w r cs thermal resistance, case to sink typ. 0.5 - r ja thermal resistance, junction to ambient 62.5 62.5 *drain current limited by maximum junction temperature
fdp8n50nz / fdpf8n50n zt n-channel mosfet fdp8n50nz / FDPF8N50NZT rev. a www.fairchildsemi.com 2 package marking and ordering information electrical characteristics t c = 25 o c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics device marking device package reel size tape width quantity fdp8n50nz fdp8n50nz to-220 - - 50 FDPF8N50NZT FDPF8N50NZT to-220f - - 50 symbol parameter test conditions min. typ. max. units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0v, t c = 25 o c 500 - - v ? bv dss ? t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 o c-0.5-v/ o c i dss zero gate voltage drain current v ds = 500v, v gs = 0v - - 1 a v ds = 400v, t c = 125 o c--10 i gss gate to body leakage current v gs = 25v, v ds = 0v - - 10 a v gs(th) gate threshold voltage v gs = v ds , i d = 250 a3.0-5.0v r ds(on) static drain to source on resistance v gs = 10v, i d = 4a - 0.77 0.85 ? g fs forward transconductance v ds = 20v, i d = 4a (note 4) -6.3-s c iss input capacitance v ds = 25v, v gs = 0v f = 1mhz - 565 735 pf c oss output capacitance - 80 105 pf c rss reverse transfer capacitance - 5 10 pf q g(tot) total gate charge at 10v v ds = 400v,i d = 8a v gs = 10v (note 4, 5) -1418nc q gs gate to source gate charge - 4 - nc q gd gate to drain ?miller? charge - 6 - nc t d(on) turn-on delay time v dd = 250v, i d = 8a r g = 25 ? , v gs = 10v (note 4, 5) -1745ns t r turn-on rise time - 34 80 ns t d(off) turn-off delay time - 43 95 ns t f turn-off fall time - 27 60 ns i s maximum continuous drain to source diode forward current - - 8 a i sm maximum pulsed drain to source diode forward current - - 30 a v sd drain to source diode forward voltage v gs = 0v, i sd = 8a - - 1.4 v t rr reverse recovery time v gs = 0v, i sd = 8a di f /dt = 100a/ s (note 4) - 300 - ns q rr reverse recovery charge - 1.9 - c notes: 1. repetitive rating: pulse width limited by maximum junction temperature 2. l = 3.8mh, i as = 8a, v dd = 50v, r g = 25 ? , starting t j = 25 c 3. i sd 8a, di/dt 200a/ s, v dd bv dss , starting t j = 25 c 4. pulse test: pulse width 300 s, duty cycle 2% 5. essentially independent of operating temperature typical characteristics
fdp8n50nz / fdpf8n50n zt n-channel mosfet fdp8n50nz / FDPF8N50NZT rev. a www.fairchildsemi.com 3 typical performance characteristics figure 1. on-region characteristics figure 2. transfer characteristics figure 3. on-resistance variation vs. figure 4. body diode forward voltage drain current and gate vo ltage variation vs. source current and temperature figure 5. capacitance characteristics figure 6. gate charge characteristics 0.03 0.1 1 10 20 0.03 0.1 1 10 30 *notes: 1. 250 s pulse test 2. t c = 25 o c v gs = 15.0 v 10.0 v 8.0 v 7.0 v 6.5 v 6.0 v 5.5 v i d , drain current[a] v ds , drain-source voltage[v] 246810 0.1 1 10 30 -55 o c 150 o c *notes: 1. v ds = 20v 2. 250 s pulse test 25 o c i d , drain current[a] v gs , gate-source voltage[v] 0369121518 0.4 0.8 1.2 1.6 2.0 *note: t c = 25 o c v gs = 20v v gs = 10v r ds(on) [ ? ] , drain-source on-resistance i d , drain current [a] 0.4 0.8 1.2 1.6 2.0 2.4 1 10 100 *notes: 1. v gs = 0v 2. 250 s pulse test 150 o c i s , reverse drain current [a] v sd , body diode forward voltage [v] 25 o c 0.1 1 10 30 0 300 600 900 1200 c oss c iss c iss = c gs + c gd ( c ds = shorted ) c oss = c ds + c gd c rss = c gd *note: 1. v gs = 0v 2. f = 1mhz c rss capacitances [pf] v ds , drain-source voltage [v] 03691215 0 2 4 6 8 10 *note: i d = 8a v ds = 100v v ds = 250v v ds = 400v v gs , gate-source voltage [v] q g , total gate charge [nc]
fdp8n50nz / fdpf8n50n zt n-channel mosfet fdp8n50nz / FDPF8N50NZT rev. a www.fairchildsemi.com 4 typical performance characteristics (continued) figure 7. breakdown voltage variation figure 8. on-resistance variation vs. temperature vs. temperature figure 9. maximum safe operating area figure 10. maximum safe operating area - fdp8n50nz - FDPF8N50NZT figure 11. maximum drain current vs. case temperature -100 -50 0 50 100 150 0.8 0.9 1.0 1.1 1.2 *notes: 1. v gs = 0v 2. i d = 250 a bv dss , [normalized] drain-source breakdown voltage t j , junction temperature [ o c ] -100 -50 0 50 100 150 200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 *notes: 1. v gs = 10v 2. i d = 4a r ds(on) , [normalized] drain-source on-resistance t j , junction temperature [ o c ] 1 10 100 1000 0.01 0.1 1 10 50 10 s 100 s 1ms 10ms i d , drain current [a] v ds , drain-source voltage [v] operation in this area is limited by r ds(on) *notes: 1. t c = 25 o c 2. t j = 150 o c 3. single pulse dc 1 10 100 1000 0.01 0.1 1 10 50 10 s 100 s 1ms 10ms i d , drain current [a] v ds , drain-source voltage [v] operation in this area is limited by r ds(on) *notes: 1. t c = 25 o c 2. t j = 150 o c 3. single pulse dc 25 50 75 100 125 150 0 2 4 6 8 10 i d , drain current [a] t c , case temperature [ o c ]
fdp8n50nz / fdpf8n50n zt n-channel mosfet fdp8n50nz / FDPF8N50NZT rev. a www.fairchildsemi.com 5 typical performance characteristics (continued) figure 12. transient thermal response curve - fdp8n50nz figure 13. transient thermal response curve - FDPF8N50NZT 10 -5 10 -4 10 -3 10 -2 10 -1 1 0.01 0.1 1 2 0.01 0.1 0.2 0.05 0.02 *notes: 1. z jc (t) = 0.96 o c/w max. 2. duty factor, d= t 1 /t 2 3. t jm - t c = p dm * z jc (t) 0.5 single pulse thermal response [ z jc ] rectangular pulse duration [sec] t 1 p dm t 2 10 -5 10 -4 10 -3 10 -2 10 -1 11010 2 10 3 0.01 0.1 1 0.01 0.1 0.2 0.05 0.02 *notes: 1. z jc (t) = 3.1 o c/w max. 2. duty factor, d= t 1 /t 2 3. t jm - t c = p dm * z jc (t) 0.5 single pulse thermal response [ z jc ] rectangular pulse duration [sec] 5 t 1 p dm t 2
fdp8n50nz / fdpf8n50n zt n-channel mosfet fdp8n50nz / FDPF8N50NZT rev. a www.fairchildsemi.com 6 gate charge test circuit & waveform resistive switching test circuit & waveforms unclamped inductive switching test circuit & waveforms
fdp8n50nz / fdpf8n50n zt n-channel mosfet fdp8n50nz / FDPF8N50NZT rev. a www.fairchildsemi.com 7 peak diode recovery dv/dt test circuit & waveforms dut v ds + _ driver r g sam e type as d u t v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l i sd 10v v gs ( d riv e r ) i sd ( dut ) v ds ( dut ) v dd body d iode forw ard volta g e d rop v sd i fm , body d iode forw ard c urrent body d iode r everse c urrent i rm body d iode r ecovery dv/dt di/dt d = g ate pulse w idth gate pulse period -------------------------- dut v ds + _ driver r g sam e type as d u t v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l l i sd 10v v gs ( d riv e r ) i sd ( dut ) v ds ( dut ) v dd body d iode forw ard volta g e d rop v sd i fm , body d iode forw ard c urrent body d iode r everse c urrent i rm body d iode r ecovery dv/dt di/dt d = g ate pulse w idth gate pulse period -------------------------- d = g ate pulse w idth gate pulse period --------------------------
fdp8n50nz / fdpf8n50n zt n-channel mosfet fdp8n50nz / FDPF8N50NZT rev. a www.fairchildsemi.com 8 mechanical dimensions to-220
fdp8n50nz / fdpf8n50n zt n-channel mosfet fdp8n50nz / FDPF8N50NZT rev. a www.fairchildsemi.com 9 package dimensions dimensions in millimeters to-220f potted * front/back side isolation voltage : 4000v
fdp8n50nz / fdpf8n50 nzt n-channel mosfet fdp8n50nz / FDPF8N50NZT rev. a www.fairchildsemi.com 10 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes wi thout further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fai rchild semiconductor corporation. as used herein: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform c an be reasonably expected to cause the failure of the life su pport device or system, or to affect its safety or effectiveness. product status definitions definition of terms accupower? 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